Digital Systems is 8–12 items, the biggest computer-side area of the E&C specification and tied with Power Systems. It runs from number bases and Boolean algebra up to state machines and the timing that makes them work.
Updated Oct 29, 2026 · Not affiliated with NCEES.
ExamFE Electrical and Computer
items · Digital Systems8–12
problems on this page16
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What the area covers
Eight subtopics in the July 2020 specification:
Number systems: binary, octal, hex, signed representations.
Boolean logic: the algebra and its theorems.
Logic gates and circuits: combinational building blocks such as decoders and multiplexers.
Logic minimization: SOP and POS forms, Karnaugh maps.
Flip-flops and counters.
Programmable logic devices and gate arrays.
State machine design.
Timing: timing diagrams, asynchronous inputs, race conditions and hazards.
16 digital systems problems
0 / 16 answered · 0 correct
Question 1 of 16 · Digital Systems · 8–12 items
What is the decimal value of the 8-bit two's complement number 11110100?
Given
8-bit two's complement word = 11110100
Find
Decimal value
Solution
11110100 → invert → 00001011 → +1 → 00001100 = 12
value = −12 (check: 244 − 256 = −12)
This reads the word as sign-magnitude: sign bit 1, magnitude 1110100 = 116.
Invert 11110100 → 00001011 and add 1 → 00001100 = 12, so the value is −12.
This inverts the bits but forgets to add 1 (one's complement).
This reads the word as an unsigned number; the leading 1 marks a negative two's complement value.
Question 2 of 16 · Digital Systems · 8–12 items
A synchronous pipeline stage uses a flip-flop with clock-to-Q delay of 12 ns, followed by combinational logic having a worst-case propagation delay of 20 ns. The flip-flop setup time is 5 ns and maximum clock skew is 2 ns. What is the maximum allowable clock frequency for the stage (in MHz)?
This leaves out the 2 ns clock skew (T = 37 ns); worst-case skew shortens the usable period.
This leaves out both setup time and skew (T = 32 ns).
This counts only the 20 ns of combinational logic.
Question 3 of 16 · Digital Systems · 8–12 items
Consider the combinational function F = A B C + A' B C + A B' C'. A static-1 hazard can occur when input A switches while B and C are both 1. Which consensus (product) term, when added to F, will eliminate that static-1 hazard?
Solution
ABC + A'BC → consensus term BC
With B = C = 1 the term BC stays at 1 while A changes, so no glitch.
A C is not implied by F (A = 1, B = 0, C = 1 gives F = 0), so adding it changes the function.
A B' is not implied by F (A = 1, B = 0, C = 1 gives F = 0), so adding it changes the function, and it does not cover the B = C = 1 transition anyway.
A' B' is not implied by F (A = B = 0 gives F = 0), so it would change the logic.
ABC and A'BC differ only in A; their consensus BC holds F at 1 while A switches with B = C = 1.
Question 4 of 16 · Digital Systems · 8–12 items
A 4-variable function F(A, B, C, D) equals 1 for minterms m(1, 3, 7, 11, 15) and has don't-care conditions d(2, 5, 10, 14). What is the minimal sum-of-products expression?
Given
Minterms = m(1, 3, 7, 11, 15)
Don't-cares = d(2, 5, 10, 14)
Find
Minimal SOP expression
Solution
Quad on column CD = 11: m3, m7, m11, m15 → CD Quad m1, m3, m5 (d), m7 → A'D
F = CD + A'D
This leaves m7 (0111) uncovered: A'B'D needs B = 0 and ACD needs A = 1.
This covers every minterm but is not minimal: with don't-care m5, the pair m1–m3 grows into the quad m1, m3, m5, m7 = A'D.
CD covers m3, m7, m11, m15; the quad m1, m3, m5 (don't-care), m7 gives A'D. Two terms, four literals.
CD' covers m6, which is neither a minterm nor a don't-care, so F would be wrong there.
Question 5 of 16 · Digital Systems · 8–12 items
Convert the hexadecimal number A3F to decimal.
Given
Hexadecimal number = A3F
Find
Decimal equivalent
Solution
A3F16 = 10 × 162 + 3 × 161 + 15 × 160
= 2560 + 48 + 15 = 2623
This weights the digits by powers of 10 (10 × 100 + 3 × 10 + 15) instead of powers of 16.
This reverses the digit order, weighting F by 256 and A by 1.
Question 6 of 16 · Digital Systems · 8–12 items
Simplify the Boolean expression: F = AB + AB'
Solution
AB + AB' = A(B + B') = A
This keeps only the first term; AB' also adds the cases with B = 0.
B cancels out of the expression; F is 1 whenever A = 1, whatever B is.
This turns the common factor into a sum; factoring A out leaves B + B' = 1, not B.
AB + AB' = A(B + B') = A · 1 = A.
Question 7 of 16 · Digital Systems · 8–12 items
What is the minimum number of flip-flops needed to build a modulo-12 counter?
Given
Counter modulus = 12
Find
Number of flip-flops
Solution
2n ≥ 12 → n = ⌈log2 12⌉ = 4
Three flip-flops give only 23 = 8 states, fewer than the 12 needed.
The minimum n satisfies 2n ≥ 12: 24 = 16, so 4 flip-flops (with 4 unused states).
Five flip-flops give 32 states; four are already enough.
Twelve is the count for a ring counter (one flip-flop per state), not the minimum.
Question 8 of 16 · Digital Systems · 8–12 items
By De Morgan's theorem, (A + B)' is equivalent to:
Solution
(A + B)' = A'·B'
De Morgan: (A + B)' = A'B'; the OR becomes AND and each input is complemented.
This is the complement of a product, (AB)'; complementing a sum gives a product of complements.
This drops the complements; AB is 1 only when both inputs are 1.
Only B is complemented here; De Morgan complements every literal.
Question 9 of 16 · Digital Systems · 8–12 items
To make a JK flip-flop behave as a D flip-flop (Q+ = D on every rising clock edge), how should J and K be connected?
Solution
Q+ = JQ' + K'Q; with J = D, K = D': Q+ = DQ' + DQ = D
With J = 1 a flip-flop at Q = 0 always sets, even when D = 0.
D = 1 gives J = 1, K = 0 (set); D = 0 gives J = 0, K = 1 (reset). Either way Q+ = D.
From Q = 0 with D = 1 this gives J = 0, K = 0 (hold), so Q stays 0 instead of following D.
This sets on D = 0 and resets on D = 1, so Q+ = D', the inverse of what is needed.
Question 10 of 16 · Digital Systems · 8–12 items
The setup time of a flip-flop is the minimum time that:
Solution
Setup: data steady before the edge. Hold: data steady after it.
Setup time is the minimum interval the data input must be steady before the active clock edge.
This describes a clock pulse width requirement, not setup time.
Output timing is described by clock-to-Q delay; setup is a constraint on the input.
That window after the edge is the hold time.
Question 11 of 16 · Digital Systems · 8–12 items
A synchronous counter uses flip-flops clocked by the same signal. What is the primary advantage over an asynchronous (ripple) counter?
Solution
Ripple counter delay ≈ n · tpd; a synchronous counter settles in about one tpd plus the gating delay.
Clocking every flip-flop on every edge usually costs more power, not less.
A synchronous counter needs extra gating logic, so it is more complex than a ripple counter.
All flip-flops change on the same edge, so the delay does not add up stage by stage as in a ripple counter.
Both types need the same number of flip-flops for the same modulus.
Question 12 of 16 · Digital Systems · 8–12 items
A race condition in a digital circuit occurs when:
Solution
Race: the outcome depends on the relative arrival order of changing signals.
A long gate chain adds delay, but delay alone is not a race; the race is between paths.
An excessive clock rate causes setup violations, a different timing failure.
Supply instability causes noise and logic-level errors, not a race between signals.
In a race, two signals change at nearly the same time and the result depends on which arrives first.
Question 13 of 16 · Digital Systems · 8–12 items
A 4-to-1 multiplexer has select lines S1S0 = 10. Which data input is routed to the output?
Solution
S1S0 = 102 = 2 → Y = D2
D0 is selected by S1S0 = 00.
D3 is selected by S1S0 = 11.
S1S0 = 10 is binary 2, so input D2 is routed to the output.
D1 is selected by S1S0 = 01; this reads the select bits in reverse order.
Question 14 of 16 · Digital Systems · 8–12 items
A T flip-flop toggles its output when T = 1. If a T flip-flop starts at Q = 0 and receives three clock pulses with T = 1, what is the final state of Q?
Solution
Q+ = T ⊕ Q; 0 → 1 → 0 → 1
Each pulse toggles Q: 0 → 1 → 0 → 1, so Q = 1 after three pulses.
With T = 1 the next state is always defined: Q+ = Q'.
An even number of toggles would return Q to 0; three toggles leave it at 1.
Q alternates between pulses, but the question asks for the state after the third pulse, which is a definite value.
Question 15 of 16 · Digital Systems · 8–12 items
A logic gate has the truth table: Output = 1 only when both inputs are 0. This gate is:
Solution
NOR: Y = (A + B)' = 1 only for A = B = 0
AND outputs 1 only when both inputs are 1.
NOR = (A + B)' is 1 only when neither input is 1, that is, when both are 0.
NAND outputs 0 only when both inputs are 1, so it is 1 in three of four rows.
XOR outputs 1 when the inputs differ, and 0 when both are 0.
Question 16 of 16 · Digital Systems · 8–12 items
A 3-to-8 decoder with active-high outputs has inputs A2A1A0 = 101. Which output line is asserted?
Solution
A2A1A0 = 1012 = 5 → Y5 asserted
Y4 corresponds to 100; the least significant bit A0 = 1 adds one.
Y3 corresponds to input 011.
Y6 corresponds to 110, which would need A1 = 1 and A0 = 0.
101 in binary is 4 + 0 + 1 = 5, so output Y5 goes high.
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What to have automatic
Signed numbers: n bits in two’s complement span −2n−1 to 2n−1 − 1; the range is not symmetric.
K-maps: groups of 1, 2, 4 or 8 cells, wrapping around the edges; don’t-cares join a group only when they make it bigger.
Sequential timing: the clock period has to cover the flip-flop’s clock-to-output delay, the slowest logic path and the next flip-flop’s setup time.
State machines: in a Moore machine the outputs depend only on the state; in a Mealy machine they also depend on the inputs, so they can change between clock edges.
The FE Reference Handbook keeps its Finite State Machine material in the Mathematics chapter, not in the electrical chapter (NCEES errata notice). Search there when a state-diagram question needs notation.
Common traps in digital systems
SOP or POS. Sum of products groups the 1s; product of sums groups the 0s and complements each variable in the sum terms.
Setup or hold. Setup is the time before the clock edge, hold the time after it; a hold violation does not go away by slowing the clock.
Base conversion by hand. Converting a hex number through decimal invites errors; go hex to binary four bits at a time.
Gray code or binary. Gray code changes one bit per step; do not do arithmetic on it as if it were binary.
Active-low signals. A bubble on an input or output flips what “asserted” means.
Sources: Mano and Ciletti, Digital Design; Wakerly, Digital Design: Principles and Practices.
How it connects to other areas
Processors, memory and interfacing built from these blocks are Computer Systems. Discrete math (sets, logic, graphs) is part of the Mathematics area on the FE practice test. Transistor-level gate behavior belongs to Electronics.