FE and PE Exam

FE Electrical and Computer · areas 16, 14 and 17

Computer systems, networks and software

Three areas of the specification share this page: Computer Systems (5–8 items), Computer Networks (4–6 items) and Software Engineering (4–6 items). Together they are 13 to 20 questions, and with Digital Systems they make up the computer half of the exam.

Updated Oct 29, 2026 · Not affiliated with NCEES.

What Computer Systems covers

Three subtopics in the July 2020 specification:

  • Microprocessors: instruction execution, pipelining, performance.
  • Memory technology and systems: caches, main memory, virtual memory.
  • Interfacing: I/O, interrupts, DMA, buses.

18 computer systems, networks and software problems

0 / 18 answered · 0 correct
Question 1 of 18 · Computer Networks · 4–6 items

A network switch operates primarily at which OSI layer?

Solution

A switch learns MAC addresses and forwards frames: OSI Layer 2 (data link).

Layer 1 devices, such as hubs and repeaters, regenerate bits without reading addresses.
Layer 4 handles end-to-end ports and segments (TCP/UDP), which a switch does not process.
A switch forwards frames by MAC address, a data link (Layer 2) function.
Routing between networks by IP address is the router's job; a plain switch does not read IP headers.
Question 2 of 18 · Computer Networks · 4–6 items

A single TCP connection crosses a 100 Mbps link with a measured round-trip time (RTT) of 40 ms. The advertised receive window is 64 KB (65,536 bytes), and window scaling is not used. Assuming negligible packet loss, what is the maximum achievable throughput of this flow?

Given
  • Link rate = 100 Mbps
  • Round-trip time RTT = 40 ms
  • Receive window W = 64 KB (no window scaling)
FindMaximum TCP throughput (Mbps)

Solution

Throughput ≤ W/RTT

W/RTT = (65,536 × 8 bits)/0.040 s = 13.1 Mbps < 100 Mbps

This is 65,536 bytes/0.04 s = 1.64 MB/s reported as megabits; the window is in bytes and must be multiplied by 8.
This divides by twice the RTT (80 ms); one window is delivered per round trip, not per two.
Without scaling, at most one 64 KB window is in flight per RTT: 65,536 × 8 bits/0.040 s = 13.1 Mbps, far below the link rate.
The link rate is only an upper bound; a 64 KB window drains in about 5 ms of a 40 ms round trip, so the window limits the flow.
Question 3 of 18 · Computer Networks · 4–6 items

In the OSI model, which layer is responsible for error detection and correction, flow control, and frame synchronization?

Solution

Frames, CRC error detection, and hop-by-hop flow control are OSI Layer 2 (data link) functions.

Transport also controls flow, but end to end, on segments; frame synchronization is a link function.
The network layer handles logical addressing and routing of packets between networks.
The physical layer moves raw bits over the medium; it has no notion of frames.
Framing, frame-level error detection (CRC), and link flow control are the data link layer's functions.
Question 4 of 18 · Computer Networks · 4–6 items

A fully connected mesh network has 10 nodes. How many direct links are required?

Given
  • Number of nodes n = 10
FindNumber of direct links

Solution

L = n(n − 1)/2 = 10 × 9/2 = 45

Each of the n(n − 1)/2 node pairs needs its own link: 10 × 9/2 = 45.
This is n(n + 1)/2, which adds a self-link for every node.
This is n(n − 1) = 90, counting each link twice, once from each end.
This is n2, which also counts a link from each node to itself.
Question 5 of 18 · Computer Networks · 4–6 items

Which TCP/IP layer corresponds most closely to the combination of the OSI Session, Presentation, and Application layers?

Solution

TCP/IP has four layers; its application layer covers OSI layers 5–7.

The TCP/IP application layer absorbs the OSI session, presentation, and application layers.
The TCP/IP transport layer maps to the OSI transport layer alone.
Network access corresponds to the OSI physical and data link layers.
The internet layer matches the OSI network layer (IP routing).
Question 6 of 18 · Software Engineering · 4–6 items

A function contains three nested loops, each iterating n times. What is the time complexity?

Solution

T(n) = n · n · n = n3 → O(n3)

Three sequential loops would be O(3n) = O(n); nesting multiplies the counts.
The innermost statement runs n × n × n = n3 times.
Two nested loops give n2; the third level multiplies by n again.
A single loop is O(n); each extra nested level multiplies by n.
Question 7 of 18 · Software Engineering · 4–6 items

In software testing, what type of testing examines the internal structure and implementation details of the code?

Solution

White-box = structure-based (statement, branch, path coverage); black-box = specification-based.

Integration testing checks how modules work together; it can be done either way and is defined by scope, not by code visibility.
Acceptance testing checks the system against user requirements, usually as a black box.
White-box (structural) testing designs tests from the code's internal paths, branches, and statements.
Black-box testing works from the specification only, without looking at the code.
Question 8 of 18 · Software Engineering · 4–6 items

What is the cyclomatic complexity of this function? int f(int x) { if (x > 0) if (x % 2 == 0) doA(); else doB(); for (i = 0; i < 10; i++) if (check(i)) doC(); return 0; }

Given
  • Function: if (x > 0) if (x % 2 == 0) doA(); else doB(); for (i = 0; i < 10; i++) if (check(i)) doC();
FindCyclomatic complexity V(G)

Solution

V(G) = P + 1, P = number of binary decisions

P = 4 (two ifs, the loop test, the if inside the loop) → V(G) = 5

This counts the else branch as a separate decision; an if-else is one binary decision.
Decisions: if (x > 0), if (x % 2 == 0), the for condition, and if (check(i)) = 4; V(G) = 4 + 1 = 5.
This is the number of decision points; V(G) adds 1 to it.
This counts only the three if statements and forgets the for loop and the +1.
Question 9 of 18 · Software Engineering · 4–6 items

What is the worst-case time complexity of the bubble sort algorithm when sorting an array of n elements?

Solution

comparisons = (n − 1) + (n − 2) + … + 1 = n(n − 1)/2 → O(n2)

That is the bound for merge sort or heapsort, not bubble sort.
Logarithmic time fits binary search, not a sort that must look at every element.
O(n) is bubble sort's best case (already sorted, with an early-exit flag), not its worst case.
In the worst case (reverse order) bubble sort makes about n2/2 comparisons and swaps.
Question 10 of 18 · Software Engineering · 4–6 items

Which data structure follows the Last-In-First-Out (LIFO) principle?

Solution

Stack: push/pop at one end → LIFO.

A stack adds and removes at the top only: the last item pushed is the first popped.
A queue is first-in-first-out (FIFO).
A binary tree is a hierarchical structure with no inherent LIFO order.
A linked list can implement a stack, but by itself it imposes no access order.
Question 11 of 18 · Computer Systems · 5–8 items

A 5-stage pipelined processor operates at 2 GHz clock frequency. If a program contains 1000 instructions and encounters 50 pipeline stalls of 2 cycles each, what is the total execution time?

Given
  • Pipeline stages k = 5
  • Clock frequency f = 2 GHz
  • Instructions n = 1000
  • Stalls = 50 of 2 cycles each
FindTotal execution time (ns)

Solution

cycles = (k − 1) + n + stall cycles = 4 + 1000 + 100 = 1104

t = cycles × Tclk = 1104 × 0.5 ns = 552 ns

This counts one cycle per instruction only, with no pipeline fill and no stall cycles.
This adds the 100 stall cycles but forgets the k − 1 = 4 cycles needed to fill the pipeline.
Cycles = (k − 1) + n + stalls = 4 + 1000 + 50 × 2 = 1104; at 2 GHz each cycle is 0.5 ns, so 1104 × 0.5 = 552 ns.
This is the cycle count read as nanoseconds; at 2 GHz a cycle lasts 0.5 ns, not 1 ns.
Question 12 of 18 · Computer Systems · 5–8 items

A direct-mapped cache has 256 lines, a block size of 16 bytes, and uses a 32-bit address. How many bits are used for the tag field?

Given
  • Cache lines = 256
  • Block size = 16 bytes
  • Address width = 32 bits
FindTag field width (bits)

Solution

offset = log2(16) = 4, index = log2(256) = 8

tag = 32 − 8 − 4 = 20 bits

This takes the whole 32-bit address as the tag, as if the cache had no index or offset fields.
This subtracts only the 4 offset bits and forgets the 8 bits that select one of 256 lines.
This subtracts only the 8 index bits and forgets the 4-bit byte offset within the block.
Offset = log216 = 4 bits, index = log2256 = 8 bits, tag = 32 − 8 − 4 = 20 bits.
Question 13 of 18 · Computer Systems · 5–8 items

A memory system has an L1 cache with 2 ns access time and a 95 % hit rate, backed by main memory with 100 ns access time. Every access first checks L1; on a miss the data is then fetched from main memory. What is the effective (average) memory access time?

Given
  • L1 access time = 2 ns
  • L1 hit rate = 95 %
  • Main memory access time = 100 ns
FindEffective memory access time (ns)

Solution

teff = tL1 + (1 − h) · tmem

teff = 2 ns + 0.05 × 100 ns = 7.0 ns

Every access checks L1 (2 ns) and 5 % also go to memory: t = 2 + 0.05 × 100 = 7.0 ns.
This is a plain average of 2 and 100 ns, which ignores the 95 % hit rate.
This swaps the rates, sending 95 % of accesses to main memory: 2 + 0.95 × 100.
This charges every access the full L1 plus memory time, as if the hit rate were zero.
Question 14 of 18 · Computer Systems · 5–8 items

A processor has a CPI (cycles per instruction) of 2.5 and operates at 1.5 GHz. What is the instruction execution rate in MIPS?

Given
  • Cycles per instruction CPI = 2.5
  • Clock frequency f = 1.5 GHz
FindExecution rate (MIPS)

Solution

MIPS = f/(CPI × 106)

MIPS = 1.5 × 109 Hz/(2.5 × 106) = 600

This multiplies the clock rate by the CPI; more cycles per instruction means fewer instructions per second.
This swaps the two numbers, 2.5/1.5 × 1000, as if the clock were 2.5 GHz and the CPI 1.5.
This assumes one instruction per clock cycle and ignores the CPI of 2.5.
MIPS = f/(CPI × 106) = 1.5 × 109/(2.5 × 106) = 600.
Question 15 of 18 · Computer Systems · 5–8 items

A virtual memory system uses 4 KB (4,096-byte) pages and 32-bit virtual addresses. How many entries are required in a single-level page table?

Given
  • Page size = 4 KB
  • Virtual address width = 32 bits
FindNumber of page table entries

Solution

offset bits = log2(4096) = 12

entries = 232 − 12 = 220 = 1,048,576

This is the table size in bytes with 4-byte entries (220 × 4), not the number of entries.
Offset = log2(4096) = 12 bits, so the virtual page number has 32 − 12 = 20 bits: 220 = 1,048,576 entries.
This divides the entry count by 4 as if each entry's 4 bytes reduced the number of entries.
This is the page size in bytes (212), the offset range inside one page, not the number of pages.
Question 16 of 18 · Computer Systems · 5–8 items

A processor runs a program in 8 s. After optimization, the program executes 20 % fewer instructions and the CPI improves from 3.0 to 2.4 at the same clock rate. What is the new execution time?

Given
  • Original execution time = 8 s
  • Instruction count reduction = 20 %
  • Original CPI = 3.0
  • New CPI = 2.4
FindNew execution time (s)

Solution

t = IC × CPI × Tclk

tnew = 8 s × 0.8 × (2.4/3.0) = 5.12 s

This subtracts the two 20 % improvements (1 − 0.2 − 0.2); the factors multiply: 0.8 × 0.8.
Time ∝ instruction count × CPI: 8 × 0.8 × (2.4/3.0) = 8 × 0.8 × 0.8 = 5.12 s.
This applies only one of the two improvements (either the 20 % fewer instructions or the lower CPI).
This inverts the CPI ratio (3.0/2.4), which cancels the instruction saving.
Question 17 of 18 · Computer Systems · 5–8 items

A buffer of 64.0 × 106 bytes must be copied from one memory region to another. Option A: a CPU copy loop that takes 4 CPU cycles per byte on a 2.5 GHz CPU. Option B: a DMA engine with a bandwidth of 5.0 × 109 bytes/s and a one-time setup overhead of 200 µs. Ignoring cache effects, how long does each option take, and which finishes sooner?

Given
  • Buffer size = 64.0 × 106 bytes
  • CPU copy cost = 4 cycles per byte
  • CPU clock f = 2.5 GHz
  • DMA bandwidth = 5.0 × 109 bytes/s
  • DMA setup overhead = 200 µs
FindCopy time of each option (ms) and the faster one

Solution

tCPU = (64 × 106 B × 4 cycles/B)/(2.5 × 109 cycles/s) = 102 ms

tDMA = 0.2 ms + 64 × 106 B/(5.0 × 109 B/s) = 0.2 + 12.8 = 13.0 ms

This takes the 200 µs setup as 200 ms.
This reads 5.0 GB/s as gigabits per second: 8 × 12.8 ms + 0.2 ms = 102.6 ≈ 103 ms, which would make the CPU marginally faster.
CPU: 64 × 106 B × 4 cycles/B/(2.5 × 109 Hz) = 102 ms. DMA: 64 × 106/(5.0 × 109) = 12.8 ms + 0.2 ms setup = 13.0 ms.
This counts one cycle per byte, 64 × 106/(2.5 × 109) = 25.6 ms; the loop takes 4 cycles per byte, so the CPU needs 102 ms. The DMA verdict is right for the wrong numbers.
Question 18 of 18 · Computer Systems · 5–8 items

In an interrupt-driven I/O system, which of the following best describes the purpose of an interrupt vector?

Solution

Interrupt vector = the address (or table entry) of the service routine the CPU jumps to.

Priority is set by the interrupt controller or priority logic, not by the vector.
No counter is involved; a vector is an address (or an index into a table of addresses).
The return address is saved on the stack (or a link register) when the interrupt is taken; that is not the vector.
The vector points the processor to the entry address of the service routine for that interrupt source.

Answer every question to see your score

Processors and memory

Performance questions are one equation used every way round:

CPU time = instruction count × CPI/clock rate

Memory questions are address arithmetic: split the address into tag, index and offset, where the offset bits come from the block size and the index bits from the number of sets. Watch the definitions of average access time: one convention adds the miss penalty to the hit time, t = thit + (miss rate)·tpenalty; another weights the two levels, t = h·tcache + (1 − h)·tmemory. They give different numbers; use the one the stem defines.

Computer networks

A separate area of the specification, 4–6 items. Its six subtopics:

  • Routing and switching.
  • Topologies: mesh, ring, star.
  • Network types: LAN, WAN, the internet.
  • Models: the OSI and TCP/IP layer stacks.
  • Intrusion detection and prevention: firewalls, endpoint and network detection. Detection alerts; prevention blocks.
  • Security: port scanning, network and web vulnerability testing, penetration testing, and the security triad of confidentiality, integrity and availability.

The security subtopics are the main reason pre-2020 books fall short here: the 2014 outline listed routing and switching, topologies, frameworks and models, and LANs, with no security. For subnetting, an h-bit host field gives 2h − 2 usable hosts, because the network and broadcast addresses are reserved.

Software engineering

A separate area of the specification, 4–6 items, and the successor of the 2014 Software Development area. Its three subtopics:

  • Algorithms: sorting, searching, complexity and big-O.
  • Data structures: lists, trees, vectors, structures, arrays.
  • Implementation: iteration, conditionals, recursion, control flow, scripting and testing.

Code appears as short pseudocode. Trace it by hand with a small input and a table of variable values; that is faster than reasoning about it in your head.

Common traps in computer systems and software

  • Byte or word addressing. Address counts and offsets change by a factor of the word size.
  • Bits or bytes. Network rates are in bits per second, memory sizes in bytes; a factor of 8 hides in any problem that mixes them.
  • Worst or average case. Quicksort averages n·log n but is n2 in the worst case; binary search is log n only on sorted data.
  • Off-by-one. Check whether a loop bound is inclusive; trace the first and last iteration.
  • Recursion depth. Each call adds a stack frame; a missing or unreachable base case recurses without end.

Sources: Patterson and Hennessy, Computer Organization and Design; Kurose and Ross, Computer Networking; Cormen et al., Introduction to Algorithms.

Other E&C areas

Computer systems, quick answers

Is software engineering on the FE electrical exam?

Yes, as its own area: 4–6 questions on algorithms and big-O, data structures and implementation.

Is network security on the FE Electrical and Computer exam?

Yes, since the July 2020 specification: intrusion detection and prevention, port scanning, vulnerability and penetration testing, and the security triad are listed under Computer Networks.

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